-= PART 3 of 3 =- This is an Instructional video series that I have put together to explain the fundamental concepts and signal requirements for driving the HD44780 LCD display unit using the VHDL hardware description language. This VHDL code has been compiled to be used with the Altera Cyclone II FPGA on the Altera DE2 development board. However, you can modify the code slightly to port it to other development boards or FPGA’s and CPLD’s.

In this video I review the Clock signal requirements and also go into detail regarding the LCD core State Machine’s clock source signal: “clk_400Hz_enable” Many of you were confused why this Variable name was being used and what was the reason that a 400 Hz signal was needed. I review all of the VHDL code behind the clock signal generation and also explain how the LCD_E (LCD enable Port) is affected with these clock source signals and the reason for its use.

I try explain everything in Layman terms and use analogies with the hope that the fundamental concepts can be understood. Technically VHDL is a Hardware Description Language and is actually not a Program. It is merely a set of instructions on how to interface the the digital logic connections. With that said, I have tried to explain things in terms that can be easily understood. So just be away that VHDL is a Hardware Description language and is technically not a Software program at all.